1. Field of the Invention
The present invention relates to a high voltage semiconductor device having a level shift circuit.
2. Related Art
A power device such as an IGBT (isolated gate bipolar transistor) or a power MOSFET (insulated gate field effect transistor) is utilized in many fields such as in a motor control inverter, as well as in a power source application to a PDP (plasma display panel), a liquid crystal panel, or the like, an inverter for a home electric appliance such as an air conditioner or lighting unit, and the like.
Heretofore, the drive and control of the power device has been carried out by an electronic circuit configured by combining semiconductor elements such as a photocoupler and electronic parts such as a transformer. In recent years, however, a high voltage IC of up to a 1200V level used in an AC400V-level industrial power source or the like is put into practical use owing to the advance of LSI (large scale integration) circuit technology.
As a result of this, a gate driver IC in which are incorporated a high side gate driver and low side gate driver of a power device, furthermore, a one-chip inverter IC wherein a control circuit and a power device are integrated on one semiconductor substrate, and the like, are systematized as a high voltage IC.
The high voltage IC contributes to a total reduction in size and higher efficiency of an inverter system by a reduction in the number of parts on a mounting board. FIG. 13 is a circuit diagram of a high voltage IC in which a general level shift circuit is incorporated. The circuit diagram is a diagram in which diodes 41 and 42 are added to FIG. 8 of Japanese Patent No. 3,635,975.
In FIG. 13, reference signs 17 and 18 are IGBTs (output power devices) configuring, for example, one phase of a PWM inverter. The IGBTs 17 and 18 are connected in series between a main direct current power source (positive side) Vdc with a high voltage of, for example, DC400V and a common potential COM on the negative side of the power source. An OUT terminal is the connection point of the emitter of the IGBT 17 of the upper side arm of a bridge circuit and the collector of the IGBT 18 of the lower side arm thereof. Also, the OUT terminal is the alternating current output terminal of alternating current power generated by the IGBT 17 and IGBT 18 turning on and off complementarily.
Reference sign E2 is an auxiliary direct current power source (referred to also as a driver power source) with a low voltage of, for example, 15V, the negative terminal of which is connected to the common potential COM. Also, reference sign 20 is a driver circuit which operates under the auxiliary direct current power source E2 (a power source voltage Vcc2), and the driver circuit drives the IGBT 18 of the lower side arm to turn on and off.
As other circuit portions, there are a level shift circuit and driver circuit 16 for driving the IGBT 17 of the upper side arm of the bridge circuit, and the like. Also, there are a control circuit 61 for inputting on and off signals into each of the driver circuits 16 and 20, and the like.
A high voltage MOSFET 1 is energized by an on signal 25 with a set pulse. The on signal 25 is generated by the control circuit 61 (a low potential side low voltage circuit) to which current is supplied from a low voltage power source with the negative side (common potential COM) of the main direct current power source as a reference. The high voltage MOSFET 1, being a high voltage N channel MOSFET, turns on the IGBT 17 with a voltage drop of a load resistance 3 as a signal. A high voltage MOSFET 2 is likewise energized by inputting an off signal 26 with a reset pulse generated by the control circuit 61. The high voltage MOSFET 2, being a high voltage N channel MOSFET, turns off the IGBT 17 with a voltage drop of a load resistance 4 as a signal.
Herein, the high voltage MOSFETs 1 and 2, as well as the load resistances 3 and 4, are normally configured equal to each other in order to cause the circuit constants to coincide with each other. Constant voltage diodes 5 and 6 connected in parallel to their respective load resistances 3 and 4 have the role of limiting an excessive voltage drop of the load resistances 3 and 4 and protecting NOT circuits 8 and 9 to be described hereafter. The two high voltage MOSFETs 1 and 2 of the level shift circuit form circuit portions which input signals with the common potential COM as a reference.
Meanwhile, a circuit portion bounded by the dotted line operates using as a reference a potential of the alternating current output terminal OUT alternately following the common potential COM and the potential Vdc of the high voltage main direct current power source in accordance with a turning on and off of the output IGBTs 17 and 18. Reference sign E1 in the circuit bounded by the dotted line is an auxiliary direct current power source (referred to also as a driver power source) with, for example, 15V, and a bootstrap capacitor in a bootstrap circuit is often used. The auxiliary direct current power source E1 is such that the positive terminal is connected to a positive line Vcc1, and the negative terminal is connected to the alternating current output terminal OUT.
The NOT circuits 8 and 9 and a circuit in the subsequent stage (formed of low pass filter circuits (also abbreviated as LPFs) 30 and 31, an RS flip flop (described as an RS latch or an RS-FF) 15, a driver 16, and the like) operate with the auxiliary direct current power source E1 as a power source.
However, the power source voltage of load resistance circuits of the high voltage MOSFETs 1 and 2 wherein the upper ends of the load resistances 3 and 4 are connected to the positive line Vcc1 of the auxiliary direct current power source E1 is such that the potential of the alternating current output terminal OUT varies between the common potential COM and main direct current power source (positive side) Vdc. Consequently, the power source voltage varies between E1+Vdc and E1.
Actually, however, unshown reflux diodes are connected in parallel to the IGBTs 17 and 18, respectively, with the cathodes as the collector sides. Also, there is a case in which the potential of the alternating current output terminal OUT is of a negative value of on the order of several ten V with respect to the potential of the common potential COM due to the induced electromotive force of floating inductance associated with a PCB (Printed Circuit Board) and to negative voltage noise generated by the product of circuit inductance and di/dt flowing through the IGBTs.
Next, a description will be given of an operation of the level shift circuit. Current flows through the high voltage MOSFET 1 in response to the on signal 25 applied to the gate of the high voltage MOSFET 1, and a voltage drop occurs in the load resistance 3. When the potential of the end portion of the load resistance 3 becomes equal to or smaller than the threshold value of the NOT circuit 8, the output of the NOT circuit 8 changes to Hi. This Hi level is applied to a set terminal S of the RS latch 15 via the LPF 30. Then, an output Q of the RS latch 15 changes to Hi, and the IGBT 17 is turned on via the driver 16. At the same time (to be exact, at a point slightly before an on time in order to prevent short circuit between the arms), the IGBT 18 is turned off by a signal from the control circuit 16 via an external circuit including the driver 20.
Next, by the off signal 26 being applied to the gate of the high voltage MOSFET 2, current flows through the high voltage MOSFET 2, and a voltage drop occurs in the load resistance 4. When the potential of the end portion of the load resistance 4 becomes equal to or smaller than the threshold, the output of the NOT circuit 9 changes to Hi. This Hi level is applied to a reset terminal R21 of the RS latch 15 via the LPF 31. Then, the output Q of the RS latch 15 changes to Lo, and the IGBT 17 is turned off via the driver 16. At the same time (to be exact, at a point slightly after this off time in order to prevent short circuit between the arms), the IGBT 18 is turned on via the driver 20 by a signal from the control circuit 61.
Meanwhile, when the IGBT 18 turns off, or the IGBT 17 turns on, the capacitance between the source and drain of each high voltage MOSFET 1 and 2 is charged by a sharp potential rise dV/dt occurring at the alternating current output terminal OUT as a result of this switching. A voltage drop different from with the on signal and off signal which should originally be input into the nodes of the end portions of the load resistances 3 and 4 (the nodes of the drains of the high voltage MOSFETs 1 and 2) occurs due to current charged at this time. Then, the RS latch 15 is caused to malfunction, and the IGBT 17 is erroneously turned on. As a result of this, there is fear that short circuit between the arms of the bridge circuit is caused, or the IGBT 17 is unnecessarily turned off.
There is a possibility that the same abnormal voltage drop of the load resistances 3 and 4 occurs due to exogenous noise too, apart from the switching of the IGBTs 17 and 18. The LPFs 30 and 31 are inserted in order to prevent this kind of malfunction of the RS latch 15. The LPFs 30 and 31 have the role of removing an input signal with a small pulse width (with a high frequency) based on switching or exogenous noise as an abnormal signal.
The reason to drive the IGBT 17 to turn on and off using the on signal 25 and off signal 26 which are pulse signals, as in the circuit of FIG. 13, is as follows. In order to switch an alternating current output signal of the PWM inverter or the like at high speed, it is desirable to heighten a carrier frequency which turns on and off output switching elements (the high voltage MOSFETs 1 and 2), that is, to cause the level shift circuit to operate at high speed. Also, to heighten the carrier frequency which turns on and off the output switching elements yields the advantageous effect of reducing the size of unshown coils configuring the filter circuits. As a result of this, there is an advantage that it is possible to reduce th area of the PCB, and it is possible to realize a reduction in the size of the inverter system.
Therefore, in order to cause the level shift circuit to operate at high speed, it is necessary to shorten the time for which to charge the junction capacitance of each high voltage MOSFET 1 and 2 and to reduce level shift resistance components. In order to do this, it is required to cause a relatively high current to flow through the high voltage MOSFETs 1 and 2 for the level shift circuit. However, a power loss due to the current increases particularly when the node of the OUT terminal whose potential varies due to the switching is at a high potential.
A description will be given of a case in which, for example, the voltage of the main direct current power source (positive side) Vdc is taken to be 400V, the resistance value of the level shift load resistances is taken to be 1KΩ, and the minimum on current (a drain saturation current) of the high voltage MOSFETs 1 and 2 is taken to be 50 mA. When a signal which turns on the gate of each high voltage MOSFET 1 and 2 is driven by a pulse generator circuit, and the on period duty cycle of the reset side high voltage MOSFET 2 is an average of 10%, the average loss of the high voltage MOSFET 2 is of a value of on the order of approximately 2.0 W. Although depending on the operating frequency of the IC too, in general, when mounting on an SOP (Small Outline Package) or a QFP (Quad Flat Package), the value of 2.0 W tightens particularly in terms of the standard of high temperature side allowable dissipation.
Japanese Patent No. 3,941,206 (also referred to herein as “PTL 2”) discloses a high voltage IC in which are incorporated a high side gate driver of a power device and a level shift circuit. FIG. 14 is a plan view showing a main portion of a heretofore known high voltage MOSFET and high side drive circuit. FIG. 15 is a sectional view showing a sectional structure along the section line G-G′ of FIG. 14. FIGS. 14 and 15 are diagrams showing only one high voltage MOSFET in FIGS. 1 and 2 of PTL 2.
In PTL 2, as shown in FIGS. 14 and 15, an opening portion 221 to which a semiconductor substrate (a p−substrate 200) is locally exposed is provided between an n well region 201a (the left side on the plane) forming a level shift high voltage MOSFET and an n well region 201b (the right side on the plane) forming an isolated island region (a floating potential region). A parasitic resistance R1 of an n drain region 205 of the high voltage MOSFET and the isolated island region (right side n well region 201b) is increased by providing the opening portion 221. The parasitic resistance R1 is set to a resistance value greater than that of a load resistance element (for example, a polysilicon (poly-Si) resistance RL1) connected to the n drain region 205 and isolated island region (right side n well region 201b), and the load resistance element is used as a level shift resistance, thereby realizing a stable level shift circuit.
Only one high voltage MOSFET is described in FIG. 14. With this one-input system, the high voltage MOSFET attains an on condition for a long period, an on current continues to flow during the on period of the high voltage MOSFET, and power consumption increases.
In order to avoid this, there is proposed a two-input system wherein two high voltage MOSFETs are provided. As the two-input system is such that by transmitting an on signal and off signal in the form of pulses, it is possible to shorten the on period of the high voltage MOSFETs, and significantly reduce the power consumption of a level shifter, normally, this system is often used. A simplified HVIC is described here as corresponding to the one-input system, but it is disclosed in PTL 2 that in the two-input system too, in the same way as in the one-input system, it is possible to obtain the same advantageous effects as in the one-input system.
In FIGS. 14 and 15, reference sign 200 is the p−substrate, reference signs 201a and 201b are the n well regions, reference sign 202 is a p−offset region, reference sign 203 is an n region, reference sign 204 is a p well region, reference sign 205 is the n drain region, and reference signs 206, 215, and 216 are p+regions. Reference sign 210 shown in FIG. 14 is an n+source region, which corresponds to first and second n+source regions shown by reference signs 211 and 212 in FIG. 15. Reference signs 213 and 214 are n+regions, reference sign 221 is the opening portion, reference sign 231 is a gate electrode, reference sign 241 is a COM electrode, reference sign 242 is a drain electrode, reference sign 243 is a high potential electrode, reference sign 244 is a low potential electrode, and reference sign 251 is a high resistance region.
Also, Japanese Patent No. 3,917,211 (also referred to herein as “PTL 3”) also discloses a high voltage IC in which are incorporated a high side gate driver of a power device and a level shift circuit. In PTL 3, a level shift high voltage MOSFET and an isolated island region (a floating potential region) are connected by a high voltage interconnect wire formed on a semiconductor substrate via an insulating film. In order to do this, the semiconductor substrate exposed between the high voltage MOSFET and isolated island region is provided as a thin slit region extending from a high potential region to a ground potential region, and the high voltage MOSFET and isolated island region are completely junction isolated from one another by the slit region.
When a high potential is applied to the interconnect wire connecting the high voltage MOSFET and isolated island region, a depletion layer extending from the high voltage MOSFET and a depletion layer extending from the isolated island region are connected together. By so doing, the potential of a region below the interconnect wire to which a surface of the substrate is exposed is raised to an intermediate potential, thereby preventing breakdown of the insulating film.
As heretofore described, in FIG. 13, when turning off the IGBT 18 and turning on the IGBT 17, a sharp potential rise and so-called dV/dt surge occur at the alternating current output terminal OUT as a result of this switching, and the potential of the alternating current output terminal OUT varies enormously. Also, the potential (Vcc1) of the positive line of the auxiliary direct current power source E1 and the drain potential of the high voltage MOSFETs 1 and 2 also vary in the same way due to the potential variation of the alternating current output terminal OUT.
Hereafter, a description will be given of a malfunction occurring due to the heretofore described variation in the voltage of the alternating current output terminal OUT and the voltage of the auxiliary direct current power source E1. Firstly, in FIG. 13, the high voltage MOSFETs 1 and 2 have parasitic output capacitances 51 and 52, each formed of a source-drain capacitance Cds and a drain-substrate capacitance Cdsub, as output capacitances having a large proportion of parasitic capacitances configured when the drain potential rises. When a dV/dt surge occurs at the alternating current output terminal OUT, an excessive current (a displacement current) responding to the dV/dt flows from the positive side of the auxiliary direct current power source E1 via the parasitic output capacitances 51 and 52, and the high voltage MOSFETs 1 and 2 attain a condition in which they are apparently turned on.
In this case, an erroneous signal is generated by the displacement current flowing through the nodes connected to the drains of the on signal side high voltage MOSFET 1 and off signal side high voltage MOSFET 2. Consideration will be given of, for example, a case in which hypothetically, the parasitic output capacitance 52 of the off signal side high voltage MOSFET 2 has varied on the order of 10% more greatly than the output capacitance 51 of the high voltage MOSFET 1 due to IC manufacturing process variation.
In this case, a voltage drop caused by the product of the displacement current resulting from the parasitic output capacitance 52×dV/dt and the load resistance 4 occurs. When the potential of the end portion of the load resistance 4 reaches the threshold value of the NOT circuit 9 or below, the node connected to the drain of the high voltage MOSFET 2 outputs a Hi level signal. The reset terminal R21 of the RS latch 15 is prioritized for the Hi level signal via the LPF 31, and the output Q of the RS latch 15 changes to Lo.
As a result of this, the IGBT 17 is turned off via the driver 16 and malfunctions. A detailed description will be given of the malfunction. Firstly, a displacement current l1 flows transiently through the on signal side, and a displacement current l2 flows transiently through the off signal side, due to variation in the voltage of the alternating current output terminal OUT, and the voltage of the auxiliary direct current power source E1, caused by the dV/dt surge.
In FIG. 13, in order to cause a surge current to flow through the common potential COM, the diode 41 and 42 are connected between the drain of the on signal high voltage MOSFET 1 and the alternating current output terminal OUT, and between the drain of the off signal high voltage MOSFET 2 and the alternating current output terminal OUT, respectively.
Herein, current components flowing by way of the diodes 41 and 42 when varying due to the dV/dt surge correspond to i1 and i2 in FIG. 13. The current components flowing by way of the load resistances 3 and 4 correspond to i1′ and i2′ in FIG. 13.
Displacement currents flowing through the high voltage MOSFETs 1 and 2 are represented by l1=i1+i1′ and l2=i2+i2′ respectively. Not only does the potential of the alternating current output terminal OUT rise due to the dV/dt surge, but the potential of the positive line Vcc1 of the auxiliary direct current power source E1 also rises with the rise in the potential of the alternating current output terminal OUT.
Because of this, immediately after the potential variation due to the dV/dt surge, the minute displacement currents i1′ and i2′ flow to the common potential COM via their respective load resistances 3 and 4 and high voltage MOSFETs 1 and 2. The minute displacement current i1′ and a voltage drop at the load resistance 3, and the minute displacement current i2′ and a voltage drop at the load resistance 4, become equal to or greater than the potential difference (herein taken to be 15V) between the positive line Vcc1 of the auxiliary direct current power source E1 and the alternating current output terminal OUT. When the voltage drop at both ends of each of the load resistances 3 and 4 is 0.6V or more lower than the potential of the alternating current output terminal OUT, the displacement currents start to flow through the diodes 41 and 42 in the forward direction. That is, with a sharp dV/dt surge of on the order of several ten KV/μs, as the voltage drop at both ends of each of the load resistances 3 and 4 is 0.6V or more lower than the potential of the alternating current output terminal OUT, most of the displacement currents flow down the diodes 41 and 42, and charge the parasitic output capacitances 51 and 52 of the high voltage MOSFETs 1 and 2. However, the minute displacement currents i1′ and i2′ are dominant when a dV/dt surge of on the order of several KV/μs occurs. Note that the voltage clamp constant voltage diodes 5 and 6 connected in parallel to the load resistances 3 and 4 are taken to be at an operation voltage or below.
When the displacement currents caused by the dV/dt surge of on the order of several ten KV/μs flow down the diodes 41 and 42, and charge the parasitic output capacitances 51 and 52 of the high voltage MOSFETs 1 and 2, the voltage drop at both ends of each load resistance 3 and 4 is 15.6V or more.
Because of this, both the NOT circuits 8 and 9 output Hi signals, and the RS flip flop 15 cannot distinguish between the set signal and reset signal. Because of this, the signals are not accepted, thus not resulting in a malfunction.
However, with the dV/dt surge of several KV/μs, there is a case in which the minute displacement currents i1′ and i2′ and the voltage drops of the load resistances 3 and 4 fall just in the vicinity of the Vth (threshold) voltage of the NOT circuits 8 and 9, and are transmitted as erroneous signals.
The Vth (threshold) voltage of the NOT circuits 8 and 9 described here is attributed to the respective current drive capabilities of an unshown NMOS and PMOS of a CMOS inverter circuit configured of the NMOS and PMOS.
Assuming that the current drive capabilities of the NMOS and PMOS are equal, the Vth voltage of the NOT circuits 8 and 9 is represented by the potential difference between the positive line Vcc1 of the auxiliary direct current power source E1 and the alternating current output terminal OUT÷2=7.5(V). Herein, a description will be given of erroneous signals triggered by the displacement currents i1′ and i2′ when the on signal side and off signal side parasitic output capacitances 51 and 52 components are different from one another due to manufacturing variation, as heretofore described.
When the dV/dt surge of several KV/μs enters the alternating current output terminal OUT, one of the minute displacement currents i1′ and i2′ between the positive line Vcc1 of the auxiliary direct current power source E1 and the alternating current output terminal OUT exceeds 1.5 mA (the threshold voltage 7.5V of the NOT circuits 8 and 9÷ the load resistances 5.0KΩ).
As the Hi signal is then input into one of the NOT circuits 8 and 9, an erroneous signal is transmitted to the output Q of the RS latch 15. An estimation of on signal side and off signal side voltage drops of the erroneous signal at this time is such that, for example, when a combined capacitance Cn1 of the output capacitance 51 (Cds+Cdsub) of the high voltage MOSFET 1 is taken to be 2 pF, a combined capacitance Cn2 of the output capacitance 52 (Cds+Cdsub) of the high voltage MOSFET 2 is taken to be 2.2 pF (assuming that there is an increase of 10% due to manufacturing variation), and the load resistances 3 and 4 are taken to be 5.0KΩ, a dV/dt surge of 0.7 KV/μs enters the alternating current output terminal OUT. At this time, a voltage drop of the node connected to the on signal side (i1′ side) load resistance 3 is represented by the following expression (I′).Vs1=2×10−12×(0.7×103/(1×10−6))×5×103=7.0V  (I′)
Meanwhile, a voltage drop of the node connected to the off signal side (i2′ side) load resistance 4 is represented by the following expression (II′).Vr1=2.2×10−12×(0.7×103/(1×10−6))×5×103=7.7V  (II′)
At this time, as the voltage drop of the node connected to the off signal side load resistance 4 exceeds the threshold voltage Vth=7.5V of the NOT circuit 9, only the NOT circuit 9 erroneously outputs the Hi signal.
In order to mitigate the heretofore described erroneous signal level, it is conceivable to, for example, reduce the resistance values of the level shift load resistances 3 and 4 from 5KΩ to on the order of 1KΩ, but there is the following kind of problem. Firstly, when the on currents of the high voltage MOSFETs 1 and 2 when the load resistances 5KΩ are used are hypothetically set to a saturation current of 10 mA, it is necessary, with a load resistance of 1KΩ, to cause a saturation current of 50 mA to flow.
When the saturation current of 50 mA of the high voltage MOSFETs 1 and 2 is caused to flow, the voltage of the main direct current power source Vdc is taken to be 400V, and signals which turn on the gates of the high voltage MOSFETs 1 and 2 are hypothetically driven by a pulse generator. In this case, in particular, when the on duty cycle of the reset side high voltage MOSFET 2 is taken to be an average of 10%, a switching is performed in a condition in which the emitter potential of the IGBT 17 is high. Because of this, the average loss of he high voltage MOSFET 2 is as much as on the order to 2.0 W, thus significantly exceeding the allowable dissipation of a package for sealing the high voltage IC with resin.
Normally, the heat allowable dissipation of an SOP (Small Outline Package) with enhanced heat dissipation is on the order of 0.8 W. Because of this, in order to reduce the heat allowable dissipation to 0.8 W or below, it is necessary to shorten the on duty of the high voltage MOSFETs 1 and 2 to 4% or below.
However, when the on duty of the high voltage MOSFETs 1 and 2 is shortened, a high switching frequency of several hundred KHz to several MHz is required for a reduction in the size of a power source system in the application to power supply equipment with low and medium capacitance, an FPD (Flat Panel Display), a household electrical appliance, or the like.
At this time, the relationship with a delay time resulting from the input capacitance and output capacitance of the level shift circuit and the input capacitance of the subsequent stage, such as the buffer circuit (the NOT circuits 8 and 9, the LPFs 30 and 31, and the like) and the driver 16, can be a problem.
In the case of the kind of high voltage IC shown in FIG. 13 in which are incorporated the general level shift circuit and floating potential region, a turn-on/off transmission delay time from the load resistance circuit to the driver 16 is on the order of 100 ns to 200 ns.
This is due to the effect of the charging time of the parasitic output capacitances 51 and 52, the parasitic capacitance of the buffer circuit, or the like. That is, when the oscillation frequency of the high voltage IC is set to 1 MHz, a 10% duty falls in an on period of 100 ns, meaning that there occurs the constraint that it is not possible to set the duty to an on duty equal to or lower than the 10% duty or an off duty equal to or higher than 90%.
Because of this, even though the on and off duties of the high voltage MOSFETs 1 and 2 are driven at 4% or below in order to reduce the average loss, the problem of no on signal being transmitted occurs depending on the transmission delay time.
The signal level of an erroneous signal generated by the displacement current resulting from the dV/dt surge depends heavily on the capacitance values of the parasitic output capacitances 51 and 52 of the high voltage MOSFETs 1 and 2 described in FIG. 13, and is less affected by the NOT circuits 8 and 9 and LPFs 30 and 31, and apart from them, by a floating capacitance below a metal wiring, and the like.
Also, apart from the heretofore described malfunction mode, when the dV/dt surge is input, the period of charging the parasitic output capacitances 51 and 52 of the on signal side high voltage MOSFET 1 and off signal side high voltage MOSFET 2 is a period for which a transmission signal is not transmitted to the next stage. There is also the problem that the input/output transmission delay time of the high side drive circuit increases in a period for which this input signal and the dV/dt surge are superimposed on each other.
Therefore, it is very effective to suppress the allowable dissipation of the high voltage IC while lowering the output capacitances of the high voltage MOSFETs 1 and 2 in order to lower the displacement current which causes a malfunction and increase in transmission delay time based on the dV/vt surge.
As shown in FIGS. 14 and 15, in the heretofore described PTL 2, the drain region of the high voltage MOSFET and the high voltage isolated island region are integrated. Also, it is described that the opening portion 221 to which is exposed the p−substrate 200 is provided between the drain region 205 of the high voltage MOSFET and the high side drive circuit logic region and n+region 214 (a second pick-up region 122 in FIG. 16 to be described hereafter) which is at a potential of Vcc1. With the heretofore described PTL 2, it is possible to heighten the parasitic resistance between the drain region 205 of the high voltage MOSFET and the n+region 214 (second pick-up region 122), but the following problems arise.
FIG. 16 is a plan view showing parasitic output capacitance components of high voltage MOSFETs of a heretofore known example. As shown in FIG. 16, an output capacitance Coss (a junction capacitance C1) of each high voltage MOSFET 71 and 72 is formed between the n+drain region 213 and ground potential region (a p−well region 102) of each corresponding high voltage MOSFET 71 and 72. Further, parasitic junction capacitances C2 formed in parallel with the junction capacitance C1 exist in a breakdown voltage region 80 (HVJT; a high voltage junction terminal region) and a high side n well region 201. By so doing, a net output capacitance Ctotal of the high voltage MOSFET 71 is presented by Ctotal=C1+(2×C2), meaning that there is the problem that the output capacitance Coss of each high voltage MOSFET 71 and 72 becomes very high.
In FIG. 16, reference sign 15 is an RS flip flop (RS-FF, RS latch), reference sign 16 is a high side driver portion, reference sign 16a is a high side logic circuit portion, reference signs 30 and 31 are the low pass filter circuits (LPFs), and reference signs 71 and 72 are the high voltage MOSFETs. Also, reference sign 101 is an n−region, reference sign 102 is the p−well region, reference 103 is an n+drain region, reference sign 104 is an n buffer region, reference sign 105 is a p base region, reference sign 113 is a p+region, reference sign 114 is an n+source region, reference sign 115 is a gate electrode, reference sign 120 is a drain electrode, reference sign 122 is a second pick-up region (an n+region), reference sign 131 is a p−opening portion, and reference sign 201 is the n well region.
Also, in the heretofore described PTL 3, it is described that the breakdown voltage structure of the level shift high voltage MOSFET in the high voltage IC and the breakdown voltage structure of the high voltage isolated island region are brought together. However, in the heretofore described PTL 3, a slit region, to which is exposed the semiconductor substrate, divided perpendicularly to equipotential lines from the high potential region to the ground potential region is provided between the high voltage MOSFET and isolated island region. Because of this, the potential gradient is difficult to uniformize in the slit region inside the breakdown voltage structure, and the growth of a depletion layer is suppressed, due to which there is the problem that it is easy to locally cause electric field concentration, and it is difficult to raise a breakdown voltage. Also, the heretofore described PTL 3 does not describe the output capacitance of the high voltage MOSFET either.
Also, in order to configure the heretofore described level shift circuit of the high voltage IC, it is essential to form level shift resistances, but in the heretofore described PTLs 2 and 3, resistance elements of polysilicon are disposed in the high side drive circuit region as the level shift resistances. Because of this, it is necessary to secure load resistance formation regions corresponding to two input signals, a set signal and a reset signal. There is more than a little increase in the chip area of the high voltage IC due to this, and an increase in the number of manufacturing steps by adding a high resistance polysilicon formation step is also unavoidable.
Meanwhile, a description will be given of a case in which the resistance elements of polysilicon or the like are not used as the level shift resistances. FIG. 17 is a plan view showing another example of the main portion of the high voltage MOSFETs and high side drive circuit of the heretofore known example. When the resistance elements of polysilicon or the like are not used as the level shift resistances, it is conceivable that a parasitic resistance region of an N-type diffusion layer or N-type epitaxial layer positioned between the drains of the high voltage MOSFETs and a high potential side (the positive line of the auxiliary direct current power source E1) Vcc1 pick-up region of the high side drive circuit is used as the level shift resistances, as shown in FIG. 17.
In the two-input method, in order to prevent a malfunction due to the dV/dt surge or the like, it is ideal that the output capacitances of the set side and reset side level shift resistances and high voltage MOSFETs are equal to each other without any variation.
However, when the parasitic resistance region of the N-type diffusion layer or N-type epitaxial layer positioned between the drains of the high voltage MOSFETs and the high potential side Vcc1 pick-up region of the high side drive circuit is used as the level shift resistances, as shown in FIG. 17, the parasitic resistance varies according to a position in which is disposed the high potential side Vcc1 pick-up region of the high side drive circuit, and the absolute value of the level shift resistances changes depending on a layout.
Because of this, in the two-input method, when the set side and reset side level shift resistances vary, a difference occurs between the potential changes of the drain nodes of the set side and reset side high voltage MOSFETs when the dV/dt surge is input into the level shift circuit, and there is a possibility that an erroneous signal is transmitted to the logic circuit in the subsequent stage.
Also, the N-type diffusion layer or N-type epitaxial layer between the drains of the high voltage MOSFETs and the high potential side Vcc1 pick-up region of the high side drive circuit forms a variable resistance region which varies according to the potential condition (herein, a change from 15V to 415 v which is higher by a Vdc voltage) of the positive line Vcc1 of the auxiliary direct current power source E1.
In a condition in which the potential of the positive line Vcc1 of the auxiliary direct current power source E1 is as high as 415V, the parasitic resistance value increases due to depletion from the junction portion of the parasitic resistance region and ground potential region, and the input/output transmission delay time increases. The higher the potential dependence of the resistance value of the parasitic resistance region, the higher the U-VCC voltage dependence of the input/output transmission delay time, as a result of which the frequency of the high voltage IC cannot be made higher.